PSC-TG: RTL Power Side-Channel Leakage Assessment with Test Pattern Generation
TimeWednesday, December 8th1:52pm - 2:15pm PST
Hardware Security: Attack and Defense
DescriptionPower side-channel attacks (SCAs) pose serious threats to cryptographic implementation. Existing power side-channel leakage (PSCL) assessment techniques mostly focus on post-silicon stages, suffering from the extremely low flexibility in changing designs to address issues. In this paper, we propose our RTL-PSC TG framework which supports PSCL assessment at RTL, allowing large space for countermeasures deployment at design-level. The framework utilizes RTL information flow tracking and formal verification techniques to derive test patterns causing maximum PSCL. The first and higher-order PSCL can be quantified and analyzed at the RTL. Extensive experiments have been performed to demonstrate the effectiveness of this work.