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Presentation

SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping
TimeWednesday, December 8th3:50pm - 4:10pm PST
Location3016
Event Type
Research Manuscript
Virtual Programs
Presented In-Person
Keywords
RTL/Logic Level and High-level Synthesis
Topics
EDA
DescriptionIn this work, we first show the impact of state-of-the-art cut pruning heuristics in the resulting \textit{Quaity-of-Results} (QoR) of ASIC mapped circuits and demonstrate that it often leads to sub-optimal mapping. Then, we propose a machine-learning-based cut selection model to replace cut sorting and filtering. We benchmark our approach using the ABC tool, and demonstrate that we reduce the number of considered cuts by 24\% while improving the circuit delay by ~10\% on average (up to ~18\%), and ADP by ~7\% on average (up to 22\%), with a 2\% area penalty.