qSeq: Full Algorithmic and Tool Support for Synthesizing Sequential Circuits in Superconducting SFQ Technology
TimeTuesday, December 7th10:53am - 11:15am PST
Event Type
Research Manuscript
Virtual Programs
Presented In-Person
Emerging Device Technologies
DescriptionThis paper presents a precise definition for the level of a node in a directed cyclic graph and a polynomial time algorithm for the corresponding level assignment. This enables the challenging task of synthesizing sequential SFQ circuits such as finite state machines and linear pipeline circuits. A case study is conducted on a 3-bit counter that shows the power consumption of 44.7uW and 1.4uW using RSFQ and ERSFQ cells, respectively, with the local clock frequency of 55GHz (throughput of 11GHz), which is significantly lower than the frequencies in CMOS. Finally, more results are presented on bigger benchmark circuits.