Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks
TimeThursday, December 9th4:20pm - 4:40pm PST
Analog Design, Simulation, Verification and Test
DescriptionRecent research trends in analog layout synthesis aim for a fully automated netlist-to-GDSII design flow with minimum human efforts.
Symmetry matching between critical building blocks and devices can significantly impact the overall circuit performance.
Therefore, providing accurate symmetry constraints for automated layout synthesis tools is crucial to achieving high-quality layouts.
This paper presents a novel graph-learning-based framework leveraging unsupervised learning to recognize circuit matching structures.
The proposed framework supports both system-level and device-level symmetry constraints extraction for various large-scale analog/mixed-signal systems.
Experimental results show that our framework outperforms state-of-the-art symmetry constraint detection algorithms with remarkable accuracy and runtime improvement.