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An Automated and Process-Portable Generator for Phase-Locked Loop
Time
Location
Event Type
Research Manuscript
Virtual Programs
Hosted in Virtual Platform
Keywords
Digital and Analog Circuits
Topics
Design
DescriptionWe present the first bang-bang phase-locked loop (PLL) generator with design methodologies for various circuit blocks and system levels. The generator is fully automated and parameterized, producing the layout and schematic based on process characterization and top-level specifications. Three 14GHz PLLs are instantiated in TSMC 16nm, GF 14nm and Intel 22nm technologies, demonstrating the process portability. The short generation time of less than four days enables fast PLL design and technology porting. The PLL design fabricated in TSMC 16nm shows RMS jitter of 565.4fs and power of 6.64mW from a 0.9V supply.