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Application of Deep Reinforcement Learning to Dynamic Verification of DRAM Designs
Time
Location
Event Type
Research Manuscript
Virtual Programs
Hosted in Virtual Platform
Keywords
Design Verification and Validation
Topics
EDA
DescriptionThis paper presents a deep neural network based test vector generation method for dynamic verification of memory devices. The proposed method is built on reinforcement learning framework, where the action is input stimulus on device pins and the reward is coverage score of target circuitry. The developed agent efficiently explores high-dimensional and large action space by using policy gradient method with K-nearest neighbor search, transfer learning, and replay buffer. The generated test vectors attained the coverage score of 100% for fifteen representative circuit blocks of modern DRAM design. The output vector length was only 7% of the human-created vector length.