A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN Acceleration
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DescriptionThis paper presents a charge-sharing-based 8T SRAM in-memory-computing (IMC) architecture. In the proposed IMC approach, the multiply-accumulate (MAC) operation between multi-bit activations and weights is supported using charge-sharing technique on BL parasitic capacitances. We propose split capacitor-based 5/6-bit adjustable successive-approximation-register analog-to-digital converter (SAR-ADC) to reduce the hardware cost of analog readout circuit while supporting higher precision MAC operation. The 256×64 8T SRAM macro is implemented using 28nm CMOS process. The SRAM macro achieves 30-TOPS/W with a maximum clock frequency of 125MHz at 1.0V. It also supports voltage scaling from 0.5V to 1.1V with energy consumption ranging from 7.2-J to 25.1-J.