UMOC: Unified Modular Ordering Constraints to Unify Cycle- and Register-Transfer-Level Modeling
TimeWednesday, December 8th4:30pm - 4:50pm PST
Event Type
Research Manuscript
Virtual Programs
Presented In-Person
RTL/Logic Level and High-level Synthesis
DescriptionWe propose unified modular ordering constraints (UMOC), a novel approach that seamlessly unifies method-based cycle-level (CL) modeling and signal-based register-transfer-level (RTL) modeling. Motivated by the challenges in state-of-the-art CL modeling methodologies and existing CL/RTL composition attempts, UMOC successfully breaks the trade-off between model fidelity and scheduling modularity for CL modeling and provides seamless composition of CL and RTL models. Instead of requiring the designer to specify the global intra-cycle ordering of hardware processes, UMOC eliminates this burden using implicit local ordering constraints of RTL signals and explicit local ordering constraints of CL methods. We implement and evaluate UMOC in PyMTL3.