Designing a 2048-Chiplet, 14336-Core Waferscale Processor
TimeThursday, December 9th3:30pm - 4:00pm PST
Event Type
Research Manuscript
Virtual Programs
Presented In-Person
SoC, Heterogeneous, and Reconfigurable Architectures
DescriptionWaferscale processor systems can provide a large number of cores, memory capacity and bandwidth required by today's highly parallel workloads. One approach to building waferscale systems is to use a chiplet-based approach where pre-tested chiplets are integrated on a passive silicon-interconnect wafer. This technology allows heterogeneous integration and can provide significant performance and cost benefits. However, designing such a waferscale system has several challenges such as power delivery, clock distribution, waferscale-network design, design for testability and fault-tolerance. In this work, we discuss these challenges and the design solutions we employed to build a 2048-chiplet, 14336-core waferscale processor prototype.