High-Performance FPGA-based Accelerator for Bayesian Neural Networks
TimeThursday, December 9th11:30am - 12:00pm PST
DescriptionIn this work, we propose a novel FPGA-based hardware architecture to accelerate BNNs inferred through Monte Carlo Dropout with high hardware performance.
With the partial Bayesian inference applied, an automatic framework is also proposed,
which explores the trade-off between hardware and algorithmic performance.
Our experiments demonstrate that our hardware design can beat other state-of-the-art BNN accelerator,
and our proposed automatic framework can effective find the optimal points in the design space.