Property-driven Automatic Generation of Reduced-ISA Hardware
TimeTuesday, December 7th4:30pm - 4:50pm PST
System-on-Chip Design Methodology
DescriptionAs the diversity of computing workloads and customers continues to increase, so does the need to customize hardware at low cost for different computing needs. This work focuses on automatic customization of a given hardware through eliminating unneeded or undesired instruction set architecture (ISA) instructions. We present a property-based framework for automatically generating reduced-ISA hardware. Our framework directly operates on a given arbitrary gate-level netlist, uses property checking to identify gates that are guaranteed to not toggle if only a reduced ISA needs to be supported, and automatically eliminates these gates, generating a new design.