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MeLoPPR: Software/Hardware Co-design for Memory-efficient Low-latency Personalized PageRank
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Research Manuscript
Virtual Programs
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Keywords
Embedded System Design Methodologies
Topics
Embedded Systems
DescriptionPersonalized PageRank (PPR) is a widely used algorithm in real-world applications that requires low latency computation. Most existing works focus on algorithmic optimization for improving accuracy or global graph processing on large-scale systems for improving throughput. While minimizing local PPR latency with a tight memory budget remains unexplored, we propose a hardware-friendly multi-stage PPR with much less on-chip memory requirement through stage and linear decomposition. We also propose a hybrid CPU and FPGA accelerator that greatly shortens the latency. We evaluate our framework on both CPU and Xilinx ZCU102 FPGA, and demonstrate remarkable speedups with greatly reduced memory.