Presentation
Efficient Tunstall Decoders for Compressed Deep Neural Network
Time
Location
Event Type
Research Manuscript
Hosted in Virtual Platform
AI/ML System Design
Design
DescriptionPower and area-efficient deep neural network (DNN) designs are key in edge applications. Low bitrate DNNs, via compression or quantization, enable such designs by significantly reducing memory accesses. Lossless compression, such as Tunstall coding, can reduce the average number of bits per weight to two. It is then critical to provide hardware support for such compression to fully benefit from the resulted reduced memory requirement. In this work, we present two hardware-accelerated Tunstall decoding modules that provide streamlined decoding capabilities. Simulation and synthesis target FPGA demonstrate the superiority of our modules versus existing compression techniques for DNNs.