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Formulating Data-arrival Synchronizers in Integer Linear Programming for CGRA Mapping
Time
Location
Event Type
Research Manuscript
Virtual Programs
Hosted in Virtual Platform
Keywords
SoC, Heterogeneous, and Reconfigurable Architectures
Topics
Design
DescriptionCoarse-grained reconfigurable architecture (CGRAs) is a promising programmable platform with high-performance and high power-efficiency. Mapping an application onto an abstracted 3D-model of CGRA is a primary compilation problem. Additionally, the data synchronization can significantly influence the performance of compilation. In this work, we design two kinds of data-arrival synchronizers specifically, and formulate them in an Integer Linear Programming (ILP) mapping approach. A case study shows that employing data-arrival synchronizers can get better performance. The results of a quantitative research show that CGRAs with appropriate synchronizers can reach higher compilation success rate while using less resources.