Presentation
Enabling the Design of Behavioral Systems-on-Chip
Time
Location
Event Type
Research Manuscript
Hosted in Virtual Platform
System-on-Chip Design Methodology
EDA
DescriptionHigh-Level Synthesis (HLS) dramatically facilitates the design and verification of individual components. These components are typically the dedicated hardware accelerators used within larger systems. Unfortunately HLS, is a single process (component) synthesis method. This implies that the integration of these accelerators are often done at the RT-Level, which implies that
the system-level verification and co-design needs to be done at this low level of abstraction. This work presents an approach that enables a path to generate complete SoCs at the behavioral
level. First, through an automatic bus generator. Second, through a library of synthesizable
APIs.
the system-level verification and co-design needs to be done at this low level of abstraction. This work presents an approach that enables a path to generate complete SoCs at the behavioral
level. First, through an automatic bus generator. Second, through a library of synthesizable
APIs.