Close

Presentation

SHORE: Hardware/Software Method for Memory Safety Acceleration on RISC-V
Time
Location
Event Type
Research Manuscript
Virtual Programs
Hosted in Virtual Platform
Keywords
Embedded and Cross-Layer Security
Topics
Security
DescriptionIn this paper, we present a novel hardware/software co-design methodology consisting of a RISC-V based processor extended with new instructions and microarchitecture enhancements, enabling faster memory safety checks. A compiler is instrumented to provide security operations taking into account the changes to the processor. The system is realized by enhancing a RISC-V Rocket-chip system-on-chip (SoC). The resultant processor SoC is implemented on an FPGA and evaluated with applications from SPEC 2006 (for generic applications), MiBench (for embedded applications), and Olden suites for performance. Our security coverage using the NIST Juliet test suite shows better coverage than the software only method.