SoCCAR: Detecting SoC Security Violations Under Asynchronous Resets
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Design Verification and Validation
DescriptionModern SoC designs include several reset domains that enable asynchronous partial reset while obviating complete system boot. Unfortunately, asynchronous resets can introduce security vulnerabilities that are difficult to detect through traditional validation. In this paper, we address this problem through a new security validation framework that accounts for asynchronous resets. The framework involves (1) efficient extraction of reset-controlled events while avoiding combinatorial explosion, and (2) concolic testing for systematic exploration of the extracted design space. Our experiments demonstrate that the approach can achieve more than 99% detection accuracy and verification time of a few seconds on realistic SoC designs.