LUT-Based Optimization For ASIC Design Flow
TimeWednesday, December 8th4:10pm - 4:30pm PST
Event Type
Research Manuscript
Virtual Programs
Presented In-Person
RTL/Logic Level and High-level Synthesis
DescriptionIn this paper, we
develop a new LUT-based optimization flow tailored for
the synthesis of ASICs rather than FPGAs. We enhance LUT-mapping to consider the
literal/AIG cost of LUT-nodes. We extend traditional Boolean
methods to simplify and re-shape LUT-networks, targeting the
best AIG/mapped-network implementation.
We embed our proposed LUT-based optimization
flow, area-oriented, in a commercial synthesis tool.
Using our methodology, we improve 12 of the best-area results
in the EPFL synthesis competition. Employed in an
EDA-flow for ASICs, our LUT-optimization reduces area by -
1.80%, total negative slack by -0.39% and power by
-1.72%, after PnR, at 5% runtime cost.