TensorLib: A Spatial Accelerator Generation Framework for Tensor Algebra
Hosted in Virtual Platform
RTL/Logic Level and High-level Synthesis
DescriptionWe propose TensorLib, a framework for generating spatial hardware accelerator for tensor algebra. TensorLib uses Space-Time Transformation to compactly analyze hardware dataflows. We identify the common structures of different dataflows and build parameterized hardware module templates with Chisel. Then it select the needed hardware modules for each dataflow, connect the modules using a specified interconnection pattern, and generate the complete hardware accelerator design. TensorLib improves the productivity for the development of spatial hardware architecture, providing a rich design space for many applications. Experiments show that TensorLib can generate hardware designs with different dataflows and achieve high performance.