Skew-oblivious Data Routing for Data Intensive Applications on FPGAs with HLS
Hosted in Virtual Platform
SoC, Heterogeneous, and Reconfigurable Architectures
DescriptionAlthough HLS eases the programming of FPGAs, data buffering with BRAMs and multiple PEs need to be expressed explicitly for irregular data-intensive applications.
Data routing based designs embrace exclusive buffers for PEs for high BRAM usage efficiency. However, skew datasets may cause the workload imbalance issue.
This paper proposes a skew-oblivious data routing architecture that schedules secondary PEs to help overloaded primary PEs. With it, we further propose a framework to ease the mapping of data-intensive applications.
The results of five applications show implementations are robust to skew datasets and outperform state-of-the-art designs in both throughput and BRAM usage efficiency.