ASBP: Automatic Structured Bit-Pruning for RRAM-based NN Accelerator
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DescriptionNetwork sparsity or pruning is proved effective in promoting the efficiency of DNNs on CMOS-based processors, however, it raises additional hardware and runtime overhead to be applied in RRAM-based Computing-in-Memory accelerators. This paper proposes a reinforcement learning (RL) based bit-pruning technique to achieve structured bit-sparsity in the neural network, so that it takes significantly fewer RRAM crossbars to implement the network. The proposed structured bit-pruning technique can be applied to general weight-splitting RRAM accelerators without hardware modifications, and it outperforms the state-of-the-art bit-sparse design by 1.45x in terms of the energy efficiency in our evaluation.