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Attentional Transfer is All You Need: Technology-aware Layout Pattern Generation
Time
Location
Event Type
Research Manuscript
Virtual Programs
Hosted in Virtual Platform
Keywords
Physical Design and Verification, Lithography and DFM
Topics
EDA
DescriptionHaving a set of comprehensive VLSI layout patterns is important in researches and applications of design for manufacturability (DFM).
Many previous pattern generation methods rely on complex rule-based manual guidance or a massive number of existing patterns in the current technology node for learning,
which are both costly and with limited availability.
Instead of requiring these expensive resources,
we propose an attentional transfer-based framework learning to reuse knowledge from previous technology nodes
that should have reserved an enormous amount of layout resources.