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Network-on-Interposer Design for Agile Neural-Network Processor Chip Customization
Time
Location
Event Type
Research Manuscript
Virtual Programs
Hosted in Virtual Platform
Keywords
In-Package and On-Chip Communication and Networks-on-Chip
Topics
EDA
DescriptionChiplet based multi-die integration has been thought as a key enabler of the agile chip development flow. For 2.5D based multi-die system, Network on Interposer plays an essential role not only in the performance but also the development cost of the chips. This work proposed a reusable NoI design for agile AI chip customization. The proposed NoI design can self-adapt to the inter-die communication patterns of various neural network applications, so that the produced interposers can be reused across different AI chip specifications. Experimental results show the proposed NoI design significantly outperform the baselines in performance and overhead.