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A Complete PCB Routing Methodology with Concurrent Hierarchical Routing
Time
Location
Event Type
Research Manuscript
Virtual Programs
Hosted in Virtual Platform
Keywords
Physical Design and Verification, Lithography and DFM
Topics
EDA
DescriptionThe trend of high pin density and increasing number of layers complicates PCB routing, categorized as escape and area routing. Traditional escape routing studies do not consider the quality of routing among chip components. In this work, we proposed a complete PCB routing, including simultaneous escape routing(SER), post-SER refinement, and gridless area routing. Length matching constraints and differential pairs are satisfied in proposed flow. SER completes layer assignment and produces an escape routing assuring routable area routing. Experimental results show that our PCB routing can successfully route 7 commercial PCB designs while a commercial tool cannot complete any of them.