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MEGATRON: Software-Managed Device TLB for Shared-Memory FPGA Virtualization
Time
Location
Event Type
Research Manuscript
Virtual Programs
Hosted in Virtual Platform
Keywords
SoC, Heterogeneous, and Reconfigurable Architectures
Topics
Design
DescriptionFPGAs are being virtualized to improve resource utilization in data centers.
Memory access performance is essential to FPGA hypervisors for shared-memory FPGA platform, where accelerators access memory spontaneously.
DMA remapping with IOMMU provides a
handy solution; however, fixed IOMMU can not benefit from the reconfigurability of FPGAs. In this work, we propose MEGATRON, a hybrid address translation
service consisting of a hardware TLB and a software page table walker. By integrating MEGATRON into an existing FPGA hypervisor,
we conduct a comprehensive analysis of link performance of a multi-link CPU-FPGA platform, and demonstrate the competitiveness of the customizable translation service.