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NVCell: Standard Cell Layout in Advanced Technology Nodes with Reinforcement Learning
Time
Location
Event Type
Special Session (Research Track)
Virtual Programs
Hosted in Virtual Platform
Topics
EDA
DescriptionGenerating standard cell layouts in advanced technology nodes is challenging because of complex design rule constraints (DRCs). Previous approaches leveraged mathematical optimization methods such as SAT and MILP to find an optimum solution under those constraints. These mathematical optimization methods rely on manual expression of all design rules within an optimization framework and computationally efficient solvers. In this paper we propose a reinforcement learning (RL) based approach that does not depend on those assumptions. In our approach, a design rule checker provides feedback on DRC violations to the RL agent and the agent learns how to fix them based on the data. Based on this approach, we built a layout generator called NVCell that includes a simulated annealing-based device placer and a router based on a genetic algorithm and RL. NVCell can generate layouts with equal or lower area for over 75% of cells in an industry standard cell library.