Closing the Hardware Software CoDesign Loop with Open Source Flows
TimeMonday, December 6th10:30am - 12:00pm PST
DescriptionRecent trends in chip manufacturing resulting in a plateau in clock rates and peak power dissipation have made architecture specialization one of the most promising methods of achieving continued performance scaling. In concert with this, there has been significant growth in open-source hardware – both IP blocks as well as complete design flows. The RISC-V ISA with it’s associated software stack and many of its implementations are excellent examples of how open-source designs can begin permeating many areas of the market. However, many of these implementations are targeted point design leaving hardware designers to face familiar challenges if they wish to customize. Multiple high-level synthesis techniques and more powerful HDLs, such as Chisel, address the hardware generation portion of customization but these techniques frequently do not include the ability to generate any of the required software required to program and use your customized processor. Going further, frequently a general-purpose processor, such as RISC-V based CPU, is only a small part of a system – many implementations require custom accelerators, integration of existing IP or tailored memory systems to achieve performance targets.
This tutorial will introduce participants to multiple open-source hardware development flows to demonstrate how they can be used to accelerate their own designs. This tutorial will leverage a powerful, open-source, hardware generation and co-design environment – OpenSoC System Architect to walk participants through the creation of a basic, RISC-V like processor complete with a tailored LLVM compiler. Participants will then be shown how to extend the base ISA with a custom instruction of their definition and then re-generate their processor and compiler with their new instruction support to create a tight, co-design loop with open-source tools. Simple kernels will be provided for participants to test their new compilers against.
As a demonstration of how designers may create custom systems that go beyond ISA extensions, we will demonstrate how to attach a custom, configurable, cache coherent memory system to your RISC-V based core through the Open2C plug-in for OpenSoC System Architect.
As an open-source tool, OpenSoC System Architect is designed to be customized and extended through the use of standard plug-in interfaces. Plug-ins allow a designer to incorporate their own custom IP blocks – including accelerators, memory systems, I/O devices, etc. into the OpenSoC System Architect design flow.
At the conclusion of this tutorial participants will have a good understanding of how to use open-source hardware development flows to create their own RISC-V based processors with custom extensions and how to design their own plug-ins to incorporate additional IP as their needs dictate.