Presentation
Practical Application of AI/ML to EDA Problems
TimeMonday, December 6th10:30am - 12:00pm PST
Location3014
Event Type
Tutorial
Presented In-Person
EDA
Machine Learning/AI
Organizers
DescriptionIn this tutorial, a cross-section of industry presenters will lead attendees through case studies of real applications. Our goal is to ease the path to AI/ML adoption in EDA by bridging education, openness, and trust gaps. Starting from generic concepts (neural networks, data representation, model training, and related software tools), we will develop step-by-step AI/ML flows geared towards solving concrete problems in parasitic estimation and analog design automation.This tutorial will update the EDA end-users and tool developers on current industry advances in AI/ML for EDA. The target audience is engineers and tool developers from industry and academia who want a practical guide to using AI/ML in their daily work. Each case study will include: why is this problem important, how to discover and label the EDA-data feature set, a demonstration of the ML methodology, and practical instruction for applying these methods.
Post-layout Parasitic Estimation - Use AI/ML to quickly and conservatively estimate post-layout parasitics (eg, capacitances) from pre-layout circuit netlists. This promises to provide a fast replacement for the time-consuming layout extraction step, which can significantly reduce the time it takes for an analog design to reach market.
Neural Network Based Analog Circuit Sizing - A neural network based analog circuit sizing engine will be built in a step-by-step approach. Using python ML libraries, a free circuit simulator, a free PDK and an unsized circuit schematic, a reference model for the miller amplifier will be trained. The model will be used to optimize the amplifier performance to meet target specifications. No proprietary data is needed for this tutorial.
Analog IC Layout Generation - An ML-augmented, automated approach which greatly simplifies analog layout generation. Using schematic netlist, along with foundry design rules as inputs, this flow will handle topology-based constraint extraction, optimization, as well as subsequent place and route (PnR) steps.
Post-layout Parasitic Estimation - Use AI/ML to quickly and conservatively estimate post-layout parasitics (eg, capacitances) from pre-layout circuit netlists. This promises to provide a fast replacement for the time-consuming layout extraction step, which can significantly reduce the time it takes for an analog design to reach market.
Neural Network Based Analog Circuit Sizing - A neural network based analog circuit sizing engine will be built in a step-by-step approach. Using python ML libraries, a free circuit simulator, a free PDK and an unsized circuit schematic, a reference model for the miller amplifier will be trained. The model will be used to optimize the amplifier performance to meet target specifications. No proprietary data is needed for this tutorial.
Analog IC Layout Generation - An ML-augmented, automated approach which greatly simplifies analog layout generation. Using schematic netlist, along with foundry design rules as inputs, this flow will handle topology-based constraint extraction, optimization, as well as subsequent place and route (PnR) steps.