Tapeout of a RISC-V Crypto Chip with Hardware Trojans: A Case-Study on Trojan Design and Pre-Silicon Detectability
TimeTuesday, December 7th6:00pm - 7:00pm PST
LocationLevel 2 - Lobby
DescriptionThis work presents design and integration of four hardware Trojans (HTs) into a post-quantum-crypto-enhanced RISC-V micro controller. We cover multiple HTs ranging from a simple denial-of-service HT to a side-channel HT transmitting arbitrary information to external observers. For each HT, we give real-world estimations of the detectability by the design tools or by simulation. We conclude that some HTs are easily detected by design-tool warnings. Other powerful HTs, modifying software control flow, cause little disturbance, but require covert executable code modifications. With this work, we strengthen awareness for HT risks and present a realistic testing device for HT detection tools.