An Efficient Cell Capacitor Compact Modeling and Application for High-speed DRAM Design
TimeWednesday, December 8th6:00pm - 7:00pm PST
LocationLevel 2 - Lobby
Event Type
Networking Reception
Work-in-Progress Poster
Virtual Programs
Presented In-Person
DescriptionWe propose a compact model on the layout dependent AC impedance of the cell capacitor in the frequency range of 1k~10GHz for sub-20 nm DRAM technology node. Several layout candidates are proposed for achieving high efficiency of capacitor based on accurate model (>95%). Simulation results show that optimal layout can improve effective capacitance at 1GHz up to 12% and equivalent series resistance by 92% compared to those of conventional layout. Power supply induced jitter and peak to peak amplitude of power noise can be reduced by 56 and 54% respectively, close to those of ideal capacitor 67 and 65%