RiSA: A Systolic Array Design Reinforced with Embedded Tensor Management and Accelerated Depthwise Convolutions
TimeTuesday, December 7th6:00pm - 7:00pm PST
LocationLevel 2 - Lobby
Event Type
Networking Reception
Work-in-Progress Poster
Virtual Programs
Presented In-Person
DescriptionWe present a DNN accelerator called RiSA. RiSA is based on a systolic array, but it targets a higher area efficiency by avoiding complex datapath structures. Using a lightweight set of tensor management tasks embedded within the PE array, RiSA supports various DNN models, including convolutional neural networks and natural language processing models while maintaining a high area efficiency. RiSA also provides a novel mechanism that boosts the PE utilization for depthwise convolutions on a systolic array. Compared to Eyeriss v2, RiSA improves the area and energy efficiency for MobileNet-V2 inference by 2.13x and 1.79x, respectively.