Design Context Aware Electromigration Analysis Methodology to Overcome BEOL Interconnect Scaling Induced Reliability Risk for Advanced Process Technology
TimeTuesday, December 7th6:00pm - 7:00pm PST
LocationLevel 2 - Lobby
Event Type
Networking Reception
Work-in-Progress Poster
Virtual Programs
Presented In-Person
DescriptionAs technology nodes shrink, the effect of BEOL on chip performance is increasing. Electromigration(EM) is turning out to be the main hurdle for sign-off in high performance chip(HPC) scenarios. Therefore, more accurate electromigration models are required to optimize design and ensure smooth sign-off. In this paper, we propose a novel EM simulation flow using silicon width to consider real dimensions and layout effects. The silicon width is generally wider than drawn width, so, this flow could help increase the allowable EM current without any design change especially in minimum width, which is worst case of allowable EM current