Optimal Function Clock Aware Scan Methodology
Event Type
Designer, IP and Embedded Systems Track Presentations
Virtual Programs
Hosted in Virtual Platform
Back-End Design
DescriptionClock prefix is a necessary task for scan implementation that follows function clock path as scan clock path while existing EDA tool’s autofix inserts mux to bypass function clock path and causes extra CTS effort. To fix scan clock path to function clock path, complex clock structure (100~1000 clocks in our experience) results in difficulties on time consuming clock planning and fixing. We proposed an optimal and efficient methodology to fix DRC and let scan clock path follow function clock path with less area overhead than user's manual fixing. 28.94%~83.17% fixing point reduction can be achieved in some cases with this methodology.