Automatic Clock Gating and Closed-Loop DVFS for 4nm Exynos Mobile SoC Processor
Event Type
Designer, IP and Embedded Systems Track Presentations
Virtual Programs
Hosted in Virtual Platform
Front-End Design
DescriptionPower optimization is one of the key aspects of mobile SoC. Clock gating technique has been available for a long time, but its extent in time and space was usually limited for practical reasons. The first half of this presentation shows ACG (Automatic Clock Gating), where dynamic power consumption of any unused clock nets is removed automatically. Silicon measurement shows ACG can remove as much as 90% of dynamic power consumption for passive components, e.g. bus and DRAM components, whose clock cannot get controlled effectively by S/W. Under average use scenario, this contributes to 10~30% of power reduction.
Variation is another topic of this presentation. Static approach with guardband voltage can waste significant portion of energy for margins. Better approach is to measure real-time circuit speed and to adjust frequency and voltage accordingly. This presentation shows CPM (Critical Path Monitor) cannot be made out of replica of representative timing-critical paths. Instead, fabricated CPM after calibration can have sensitivity to variations close to that of real path. Simulation results show large portion of margin can get removed with CL-DVFS without sacrificing reliability.