DescriptionSilicon debugging is very important to know drawbacks of design and at-speed test is required to find defect on timing critical path in high speed design. Conventional transition delay fault vectors could not detect defects on timing critical path effectively. Path delay fault model was developed to detect delays on timing critical path effectively. However applying path delay fault vectors is difficult because to many paths exist in VLSI design. To reduce the target delay paths we use functional test vectors. Using the function failure point information, the number of target delay paths is dramatically reduced. Silicon test result shows that the function failure oriented path delay fault vector detects failing path with small test cost. Using enhanced fault simulation report and diagnosis, failing path can be pointed out from multiple paths. From additional analysis we can find out timing degradation of failing path caused by crosstalk effect. We also find out drawback of design based on the additional crosstalk analysis.