DescriptionThe need of minimizing power consumption on our current and next gen SoCs continues to push us to improve our power efficiency design and verification methodology. Among many power saving design techniques, dynamic clock gating (DCG) is one of the most effective method to reduce dynamic power consumption. On the other side, DCG is very hard to verify via traditional simulation approach. Since 2017, our group has adopted formal sequential equivalence checking (SEC) for dynamic clock gating verification. We have seen great ROIs in terms of design quality improvement. However, one major challenge we are facing with SEC is the inevitable inconclusive proof result due to design complexity. This has posed a risk for us to meet our SoC’s overall power requirement. This presentation proposed a very promising approach to ensure SEC full proof with two type of easy RTL modifications. It makes possible to eliminate clock gating bug escapes with minimized power tradeoff in our SoCs thus help us deliver products on time and within budget. Our current results also show that the cost to implement this approach is low which makes it practical under rapid product development schedules.