Machine Learning Based Efficient Regression Test Framework in SOC Verification
Event Type
Designer, IP and Embedded Systems Track Presentations
Virtual Programs
Hosted in Virtual Platform
Front-End Design
DescriptionSince the modern system-on-chip(SOC) is composed of hundreds of IPs, full chip level verification is essential to check functionality between IPs and validity of integration. Because full chip level verification is time consuming and requires lot of computing resources, design and verification are usually performed simultaneously to reduce time-to-market. A major challenge for the SOC verification is to quickly find bugs due to design changes with minimal resources.
In this paper, we propose the machine learning based efficient regression test framework. The proposed framework consists of two parts. The first part is prediction of failure of tests by vectorization. The second part is analysis of failed log by natural language processing technique. Proposed framework reduces regression turn around time about 25% and minimizes redundant debugging by reliable failure classification with an accuracy of up to 98%.