DescriptionClock Domain Crossing (CDC) for Asynchronous Design is a challenging verification problem in modern VLSI design. Although verification methodology for Register Transfer Level (RTL) design is already proposed and widely used, that for custom designed DRAM is not applicable due to its complex clock network. As a consequence, It makes a huge hand-work of CDC analysis by memory designers because of a lot of noise in CDC results. In this work, we first propose an effective and practical CDC verification technique using simulation-based extraction method, called Vector-driven CDC (v-CDC). The proposed technique extracts information of signal transition from simulation result by using Synopsys FSDB Writer. The technique removes most of noise in CDC results which are not presented in simulation results. Experimental results show the proposed technique significantly reduces number of CDC errors those should be verified by engineers from more than 29.4 million to 20,592. The number only requires small amount of verification effort which is far different from that of CDC verification flow of conventional RTL design.