Methodology for Accurate Analysis of Dynamic Voltage Drop Induced Clock Jitter for Improved PPA
Event Type
Designer, IP and Embedded Systems Track Presentations
Virtual Programs
Hosted in Virtual Platform
Back-End Design
DescriptionTraditionally, clock jitter (induced by dynamic voltage drop) is estimated using simplistic methods and pessimistic margins have to be included in order to prevent silicon issues. For designs that push the upper boundary of achievable PPA, it is detrimental to have such approximations and this presentation captures a methodology that was used to effectively analyze clock jitter to improve PPA.

The methodology involves multiple tools and the exchange of data between them. At a high level, we use RedHawk-SC (from Ansys) to simulate dynamic voltage drop for several clock cycles and capture the voltage stats on every single transition on each clock instance. This voltage data is then passed to Clock-FX (from Ansys), to calculate the variation of cell delay due to the dynamic voltage drop. Clock-FX is able to model the delay variation at different voltages using a SPICE-like approach to accurately estimate the jitter at the clock pins of sequential instances.

The flow enabled the design team to accurately analyze clock jitter and reduce the pessimism from earlier simplistic models. Design team was able to pinpoint the clock instances that were the highest contributors of jitter and perform specific fixes to reduce it.