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Accelerating mutation coverage measurement by using concurrent fault simulator
Time
Location
Event Type
Designer, IP and Embedded Systems Track Presentations
Virtual Programs
Hosted in Virtual Platform
Topics
Front-End Design
DescriptionMetric-driven verification (MDV) is an essential methodology for today’s IP development. We want a good metric to guarantee the quality of verification that should be automated, efficient, objective, and reliable. The mutation coverage metric provided by Synopsys Certitude™ is close to ideal except for efficiency. The key problem of mutation coverage is its very long execution time. To solve this, we propose a new method which utilizes Synopsys Z01X™ concurrent fault simulator instead of general RTL simulators to accelerate the mutation detection analysis. We confirmed the execution time for measuring mutation coverage with our method has been reduced by 84.6% compared to the conventional method. From this result, 16% reduction in total verification time can be estimated. Our method contributes to realizing higher-quality MDV for today’s advanced and complex circuit designs.