DescriptionFormal property verification has made impressive progress in the chip industry to left shift the verification cycle. End-to-end formal verification is replacing the block level simulation due to its capabilities of finding corner cases exhaustively in lesser time. However, widespread proliferation has not yet occurred and one of the main reasons is inconclusive formal analysis for end-to-end properties. Writing and getting convergence of end-to-end properties is very complex as they involve relatively longer paths and huge cone of influence (COI). This paper proposes a new method (Overlapping Checkers) for FV signoff without complex end-to-end properties. The idea behind the overlapping checkers is to break the longer path into smaller paths and reduce the COI per checker. To achieve this, we create multiple virtual partitions of the design and write end-to-end checkers for each partition. The partitioning is done in such a way that each partition overlaps with its neighbor partition. This overlapping is required to make sure no gap is left in between design and verification. We have successfully deployed the proposed overlapping checkers in multiple designs and signed-off the verification without E2E checkers. This paper talks about few of the case studies and benefits of using the proposed methodology.