Ensuring Completeness of Formal Verification with GapFree: Are we done yet?
TimeTuesday, December 7th11:22am - 11:30am PST
Event Type
Designer, IP and Embedded Systems Track Presentations
Virtual Programs
Hosted in Virtual Platform
Presented In-Person
Front-End Design
DescriptionA challenge with formal verification of RTL designs is knowing how much verification is enough. This is especially true when it comes to knowing when to stop writing additional properties. How can we achieve confidence that enough properties have been checked to verify the correctness of the design? OneSpin's GapFreeVerification methodology provides an answer to this problem. The methodology results in an automated check of the written properties to ensure that all design behaviors have been captured. In this presentation, we’ll show you how we have applied the GapFreeVerification workflow to ensure completeness of verification.