Aging Timing Analysis Based on EMPYREAN-XTime
TimeTuesday, December 7th5:00pm - 6:00pm PST
LocationLevel 2 - Exhibit Hall
Event Type
Designer, IP and Embedded Systems Track Poster Networking Reception
Virtual Programs
Presented In-Person
DescriptionReliability of integrated circuits is getting growing concern in modern semiconductor industry. However, standard cells in advanced FinFET technology are also increasingly sensitive to aging effects. Timing degradation caused by these aging effects during signal propagated in paths will directly affect the operating frequency and even lead to timing issues, reducing the reliability and life-time of the integrated circuits. In this case, Path-based aging timing simulation is of paramount importance to eliminate such timing risks and to ensure the circuits reliability.
Here, We will share our practice of using EMPYREAN-XTime to perform path-level aging timing simulations as follows:
1. Applying spice simulation to check the timing information after aging, from which we achieve true critical path verification, timing degradation measurement and accurate timing under various aging conditions.
2. Establishing a machine learning based predictor to speed up the aging timing analysis. The predictor can figure out the delay of 2000 paths within 60 s, with the normalized root mean square error of the overall prediction results less than 0.2%.