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Presentation

Signal Integrity aware HBM3 6.4Gbps interface Channel Optimization
Time
Location
Event Type
Designer, IP and Embedded Systems Track Presentations
Virtual Programs
Hosted in Virtual Platform
Topics
Back-End Design
DescriptionThe importance of channel design is increasing in the current HPC design. The HBM3 interface requires channel optimization to meet strict SI requirements. In large designs, traditional SI analysis for post-layout designs may not be possible. we proposed A pre-layout automatic routing methodology. It is ensure optimal HPC design with minimum TAT. Locate layout parameters for best SI performance with the automatic pre-layout methodology. Design repetition exploration time has been greatly reduced to 100x speed. Highly efficient and advantageous methodology make SI quality post-layout designs ensured.