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Efficient System PDN Analysis Methodat Pre-Layout Stage
Time
Location
Event Type
Designer, IP and Embedded Systems Track Presentations
Virtual Programs
Hosted in Virtual Platform
Topics
Back-End Design
DescriptionAs the core logic power is increase, the large decoupling solutions for power integrity are required. In addition, the early estimation of the required decoupling solutions is needed because of high cost due to late stage design changes. Therefore, the robust and efficient system-level power integrity analysis method at early design stage is needed. In this presentation, the efficient what-if analysis method of system-level power integrity at pre-layout stage is proposed. The proposed methods include the automatic mock-up design generation method for package substrate, the simple and accurate spice model for substrate and their automatic extraction method, and system-level power integrity analysis method at pre-layout stage to find out the initial design target. The effects of MIM capacitance and the number of package decoupling capacitors are demonstrated using the proposed method.