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Unified FW/ASIC Co-Simulation for Earlier and Accelerated Pre-Silicon Testing
Time
Location
Event Type
Designer, IP and Embedded Systems Track Presentations
Virtual Programs
Hosted in Virtual Platform
Topics
Front-End Design
DescriptionThe development of FW register sequences for SoC productization commonly requires faster platforms like FPGAs or actual silicon only available later in the development cycle. The same sequences are usually validated using SystemVerilog register abstraction layer (RAL) sequences or custom FW leading to effort duplication and difficulty in reproducing exact behavior, negatively impacting time-to-market.
This presentation describes a verification toolkit that enables FW’s C++ code to be tested in timing-accurate UVM simulations without a CPU model. The methodology promotes a CPU-agnostic firmware/ASIC Co-simulation environment resulting in faster SoC level simulations, removes controller-specific dependencies and is portable across IP level testbenches.