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Presentation

Methodology for early timing and floorplanning closure in custom circuit design
TimeMonday, December 6th1:30pm - 1:50pm PST
Location2008
Event Type
Designer, IP and Embedded Systems Track Presentations
Virtual Programs
Presented In-Person
Topics
Back-End Design
DescriptionA pre-layout methodology is disclosed that allows designers to achieve a high degree of timing and floorplanning closure during the early stages of custom macro circuit design. The methodology utilizes Electronic Design Automation (EDA) tools that facilitate an efficient, iterative process of floorplanning a macro using Placement by Instance Parameter (PIP) and generating an accurate Steiner estimated parasitic (STEP) RC netlist. This parasitic netlist is used to provide an early and accurate indication of macro performance and timing margins. Case studies reveal pre- and post-layout timing as well as macro dimension to fall typically within 10%, thus giving high confidence of timing and floorplanning closure early in the design cycle.