Close

Presentation

DIMM Level Verification Methodology for DRAM Custom DFT
Time
Location
Event Type
Designer, IP and Embedded Systems Track Presentations
Virtual Programs
Hosted in Virtual Platform
Topics
Front-End Design
DescriptionNew module & DRAM types for high performance and bandwidth are making it more difficult to confirm the whole DIMM design including internal chipset operation. DRAM manufacturer have their own DFT to supply the highest quality of products to customers. Their DFT have a different truth-table than the JEDEC standard, which can cause an operation failure when using DRAM test structure mode for DIMM testing in ATE due to insufficient consideration for new modules. In this paper, we introduce the DIMM verification method as a solution to verify DIMM design & DRAM test structure simultaneously by simulation before MTO. This method makes DIMM DUT integrated with PCB design & chipset models and uses the testbench coming from ATE test program for the complete module level simulation. Additionally, to obtain reasonable simulation time, our new system reduces the time by eliminating the redundant test items. Using this methodology, we figured out DDR5 test structure problem before MTO. We used this methodology for DDR5 RDIMM, but the system has extensibility & flexibility for other DIMM through configuration step