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A comprehensive UPF coverage methodology to avoid late Si Issues
Time
Location
Event Type
Designer, IP and Embedded Systems Track Presentations
Virtual Programs
Hosted in Virtual Platform
Topics
Front-End Design
DescriptionThe increasing presence of power management with high number of switchable power domains at earlier stages in the design cycle and its effect on functionality demands simulations at RTL stage to be power aware to ensure correctness of the power management. Also, because of the complexities related to voltage domain crossings, achieving high UPF coverage has been an issue in Client and IOTG programs which is mainly because of the lack of defined methodologies, incomplete test scenarios, incorrect modelling etc. However, attaining a high low power coverage for the verification signoff is quite necessary to ensure that all the aspect of power aware simulations is covered with the test-scenarios and there are no late Si findings. This paper proposes the comprehensive methodology to achieve high (90% and above) UPF coverage in the IOTG SoC Design and it also discusses about various low power challenges pertaining to poor UPF coverage such as lack of test scenarios, modelling of PSTs, readiness of low power specs, lack of rail sequencing validation etc.