DescriptionThere are two main types of flaws that contribute to ASIC re-spins – Functional Bugs and Clocking. Clock Domain Crossing (CDC) issues in the designs are a mix of clocking and functional bugs. A memory controller system on chip (SoC) has:
• Multiple asynchronous clock domains with complex interactions • Multiple third party IPs with multiple SoCs using different configurations A waiver or disposition-based methodology is risky and leads to silicon failures. Hence, there is a need to have an accurate construction methodology to verify WDC memory controller SoCs.
To deal with the above, we have explored a CDC methodology flow that is based on Constraints. A constraint-based CDC methodology flow allowed us to catch real issues, not masked by dirty waivers, reduce the debug effort in CDC verification and catch issues when IPs did not connect correct clock or resets from central clock or reset management unit.